1. Field of the Invention
The present invention relates to a receiving apparatus according to a communications protocol employing a packet scheme in an information processor such as a computer.
2. Description of the Related Art
FIG. 3 is a view showing a constitution of an example of packet format communication data which is received by a receiving apparatus, which is a fundamental unit of communication and shows an example of a packet used in Bluetooth. The packet is composed of an address part 51 comprising an access code, a header part 52 including packet type information, a payload part 53 comprising communication data information and an effective flag part 54 including information for judging whether or not the packet is effective. The packet is orderly comprised of the address part 51, the header part 52, the payload part 53 and the effective flag part 54 and the address part 51, the header part 52, the payload part 53 and the effective flag part 54 are consecutively communicated from the left bit (the access code) one by one.
Further, there exist packets composed of the address part 51 only, and of the address part 51 and the header part 52 in some packet types.
The address part 51 has information for specifying a destination in an environment where one or more destinations can exist. The packet type information included in the header part 52 represents the type of packet itself. As a gist of the present technology, since the header part 52 is explained covering only the packet type information included, the header part is called “a type part” in the explanation thereafter. The payload part 53 is composed of communication data for practically communicating between the mutual telecommunications apparatuses. The initial 1 or 2 bytes is called a payload header where the packet size information (length field) is included. The effective flag part 54 has information for judging whether or not any error occurs in the communication data (from the type to the payload parts) by noise, etc. when communicating.
FIG. 5 is a block diagram of a configuration of a conventional receiving apparatus. The receiving apparatus 101 is represented by a receiving apparatus disclosed in Specification of Japanese Examined Patent Publication JP-B1 3070595 and a typical one in the communications protocol of packet scheme. The receiving apparatus 101 performs a receiving operation by receiving an instruction for controlling reception from a host CPU 102. When receiving the packet, or the communication data, from a destination 103, the receiving apparatus 101 stores the necessary communication data in the receiving apparatus by judging whether or not the packet was properly received. Then, when receiving an instruction for reading the received data from the host CPU 102, the receiving apparatus has a function for outputting the received data to the host CPU 102.
The receiving apparatus 101 comprises reception clock controlling means 104 having a control function for starting or stopping clock supply to each means in the receiving apparatus 101 described later, reception means 105 for receiving the external packet data, received packet analyzing means 106 for analyzing the received packet, reception memory means 107 for stopping clock supply while the receiving apparatus is not receiving and for having a capacity that can store a plurality of received packets and received data outputting means 108 for outputting the received packet from the reception memory means 107 to the host CPU 102 when accepting an instruction to read the received packet from the host CPU 102.
The reception means 105 is equal to a physical layer in a so-called communication industry (e.g.; a physical layer typified by RF module, etc. in a radio system) and an interface.
The received packet analyzing means 106 is comprised of a received address judging means 110 for judging whether or not the received packet is transmitted to the target receiving apparatus, a received header judging means 111 for judging the packet type of received packet and a reception effective flag judging means 112 for judging whether or not the received packet based on the effective flag in the received packet is effective.
The reception memory means 107 is generally comprised of memory such as SRAM, for the capacity reason, not a register group comprised of so-called IC logic gates. The reception memory means 107 also has a function not only as so-called memory but also for managing information of received data capacity stored in memory. The management information managed by the reception memory means 107 can be read from the host CPU 102 via the received data outputting means 108.
FIG. 6 is a flow chart showing a receiving operation in the receiving apparatus 101 of FIG. 5.
In the receiving apparatus 101, by that the host CPU 102 instructs to start receiving data, the reception clock controlling means 104 controls a reception controlling clock 123 to supply the reception means 105 with a clock and the reception means 105 starts receiving the communication data transmitted from the destination 103. In a step s21, the reception clock controlling means 104 starts clock supply to each means in the receiving apparatus 101. In step 22, the reception data received by the reception means 105 is passed to the received packet analyzing means 106 via an internal received data bus 124.
In the received packet analyzing means 106, in step s23, the address part of the packet that the received address judging means 110 received is firstly extracted and whether or not the received data is transmitted to the particular receiving apparatus 101 according to the extracted address section is judged. When the packet is judged as being destined for the particular receiving apparatus 101, in step s24, the received header judging means 111 analyzes the type part so as to judge whether or not the packet is received. When the packet is judged as being a packet to be received, in step s25, the received packet is stored in the reception memory means 107 via the internal received data bus 124. After storing the packet, in step s26, the reception effective flag judging means 112 analyzes the effective flag of the received and stored packet so as to judge whether or not there is any error in the packet.
In step s26, in the case that it is judged that the proper payload could not be received by occurring troubles caused by noise, etc. when communicating, the payload stored in the reception memory means 107 is abandoned in step s27. After abandoning or the packet is judged as including no error in step s26 and the reception packet is completely received, in the case that the receiving apparatus does not receive other data, the reception clock controlling means 104 controls the reception controlling clock 123 to stop clock supply to the reception means 105 so as to stop reception as in the case of step s28 and stops clock supply to each means. Thus, electric power consumption is reduced and the packet reception is terminated. Accordingly, it can be said that communication was established by judging that the proper payload could be received in step s26.
Further, in step s23, when the receiving apparatus can not extract the address part for a certain period or the receiving apparatus judged as having received the packet which is not destined for the receiving apparatus, or in step s24, when the receiving apparatus is judged as having received the packet which is not of a type of packet to be received and communication is not established like a case that the receiving apparatus does not perform the receiving operation so far, at that time, processing is shifted to step s28 and the packet reception is terminated as mentioned above.
The packet stored in the reception memory means 107 is output to the host CPU 102 when the host CPU 102 issues the instruction for reading the received data to the receiving apparatus 101. Specifically, when the host CPU 102 outputs a request signal for reading the received data to the received data outputting means 108, the received data outputting means 108 outputs the received data stored in the reception memory means 107 to the host CPU 102 via the internal received data bus 125.
Regardless of the normal or abnormal reception situation, that is, whether or not communication was established, the conventional receiving apparatus as mentioned above starts clock supply to each means from the time of starting reception. At the time to completely receive the packet, the conventional receiving apparatus stops clock supply to each means, resulting in reduction in power consumption. Accordingly, when starting reception, a clock is also supplied to the reception memory means 107. The reception memory means 107 has not only memory but also a control circuit such as an address pointer as mentioned above. Depending on the capacity of reception memory itself, the circuit relative to the whole receiving apparatus is generally large in scale. That is, clock supply to the reception memory means 107 is directly connected with a magnitude increase in electric current consumption of the receiving apparatus 101.
Here is considered a situation before establishing communication between the mutual communication apparatuses of the destination 103 and the receiving apparatus 101. Under this situation that it is unclear when the receiving apparatus receives the communication data, the receiving apparatus 101 should periodically receive the communication data since the destination 103 might transmit the communication data. That indicates a so-called standby time for cellular telephones. In this case, in order to receive the packet that is unclear when the packet is transmitted, the host CPU 102 instructs the receiving apparatus 101 to periodically perform the receiving operation. There may be also a case where the means that can set to periodically start the receiving operation is given to the receiving apparatus 101 itself.
In consideration of such situation before establishing such communication, non-communicating time (standby time) is commandingly long with respect to the time when communication is established and the receiving operation is performed (an exchanging time of the communication data). Clock supply to the reception memory means 107 every time before establishing communication results in a large consumption of unnecessary current and a problem of electrical power consumption.